pi74fct16823t/162823/162h823t 18-bit registers 1 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 logic block diagram product features: common features: ? pi74fct16823t and pi74fct162823t are high-speed, low power devices with high current drive. ?v cc = 5v 10% ? hysteresis on all inputs ? packages available: C 56-pin 240 mil wide plastic tssop (a) C 56-pin 300 mil wide palstic ssop (v) pi74fct16823t features: ? high output drive: i oh = C32 ma; i ol = 64 ma ? power off disable outputs permit live insertion ? typical v olp (output ground bounce) < 1.0v at v cc = 5v, t a = 25c pi74fct162823t features: ? balanced output drivers: 24 ma ? reduced system switching noise ? typical v olp (output ground bounce) < 0.6v at v cc = 5v, t a = 25c pi74fct162h823t features: ? bus hold retains last active bus state during 3-state ? eliminates the need for external pull-up resistors pi74fct16823t pi74fct162823t pi74fct162h823t fast cmos 18-bit registers product description: pericom semiconductors pi74fct series of logic circuits are pro- duced in the companys advanced 0.6 micron cmos technology, achieving industry leading speed grades. the pi74fct16823t, pi74fct162823t and pi74fct162h823 are 18-bit wide registers with clock enable (xclken) and clear (xclr) controls that make these devices especially suitable for parity bus interfacing in high-performance systems. the devices can be operated as two 9-bit registers or one 18-bit register using the control inputs. signal pins are arranged in a flow-through organization for ease of layout and hysteresis is designed into all inputs to improve noise margin. the pi74fct16823t output buffers are designed with a power- off disable function allowing live insertion of boards when the devices are used as backplane drives. the pi74fct162823t has 24 ma balanced output drivers. it is designed with current limiting resistors at its outputs to control the output edge rate resulting in lower ground bounce and undershoot. this eliminates the need for external terminating resistors for most interface applications. the pi74fct162h823t has bus hold which retains the inputs last state whenever the input goes to high-impedance preventing floating inputs and eliminating the need for pull-up/down resistors. r c 1 oe d 1 clr 1 clk 1 clken 1 d 1 1 q 1 to 8 other channels r c 2 oe d 2 clr 2 clk 2 clken 2 d 1 2 q 1 to 8 other channels
pi74fct16823t/162823/162h823t 18-bit registers 2 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pin name description xdx data inputs (1) xclk c l ock inputs xclken clock enable inputs (active low) xclr asynchronous clear inputs (active low) xoe output enable inputs (active low) xqx 3-state outputs note : 1. for the pi74fct162h823t, these pins have bus hold. all other pins are standard, outputs, or i/os. product pin description product pin configuration pi74fct16823 truth table (1) inputs outputs function xoe xclr xclken xclk xdx xqx high-z h x x x x z clear l l x x x l hold l h h x x q (2) load h h l - lz hh l - hz lh l - ll lh l - hh 1. h = high voltage level l = low voltage level x = dont care z = high impedance nc = no change - = low-to-high transition 2. output level before indicated steady-state input conditions were established. 1 clr 1 1 oe 2 1 q 1 3 gnd 4 1 q 2 5 1 q 3 6 v cc 7 1 q 4 8 1 q 5 9 1 q 6 10 gnd 11 1 q 7 12 1 q 8 13 1 q 9 14 2 q 1 15 2 q 2 16 2 q 3 17 gnd 18 2 q 4 19 2 q 5 20 2 q 6 21 v cc 22 2 q 7 23 2 q 8 24 1 clk 56 1 clken 55 1 d 1 54 gnd 53 1 d 2 52 1 d 3 51 v cc 50 1 d 4 49 1 d 5 48 1 d 6 47 gnd 46 1 d 7 45 1 d 8 44 1 d 9 43 2 d 1 42 2 d 2 41 2 d 3 40 gnd 39 2 d 4 38 2 d 5 37 2 d 6 36 v cc 35 2 d 7 34 2 d 8 33 gnd 25 2 q 9 26 2 oe 27 2 clr 28 gnd 32 2 d 9 31 2 clken 30 2 clk 29 56-pin v56 a56
pi74fct16823t/162823/162h823t 18-bit registers 3 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 dc electrical characteristics (over the operating range, t a = C40c to +85c, v cc = 5.0v 10%) parameters description test conditions (1) min. typ (2) max. units v ih input high voltage guaranteed logic high level 2.0 v v il input low voltage guaranteed logic low level 0.8 v i ih input high current standard input, v cc = max. v in = v cc 1a i ih input high current standard i/o, v cc = max. v in = v cc 1a i ih input high current bus hold input (4) , v cc = max. v in = v cc 100 a i ih input high current bus hold i/o (4) , v cc = max. v in = v cc 100 a i il input low current standard input, v cc = min. v in = gnd C1 a i il input low current standard i/o, v cc = min. v in = gnd C1 a i il input low current bus hold input (4) , v cc = min. v in = gnd 100 a i il input low current bus hold i/o (4) , v cc = min. v in = gnd 100 a i bhh bus hold bus hold input (4) , v cc = min. v in = 2.0v C50 a i bhl sustain current v in = 0.8v +50 i ozh (5) high-impedance v cc = max. v out = 2.7v 1 a i ozl (5) output current v cc = max. v out = 0.5v C1 a (3-s tate o utputs ) v ik clamp diode voltage v cc = min., i in = C18 ma C0.7 C1.2 v i os short circuit current v cc = max. (3) , v out = gnd C80 C140 C200 ma i o output drive current v cc = max. (3) , v out = 2.5v C50 C180 ma v h input hysteresis 100 mv maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature .................................................................... C65c to +150c ambient temperature with power applied .................................... C40c to +85c supply voltage to ground potential (inputs & vcc only) .............. C0.5v to +7.0v supply voltage to ground potential (outputs & d/o only) ........... C0.5v to +7.0v dc input voltage ............................................................................ C0.5v to +7.0v dc output current ..................................................................................... 120 ma power dissipation .......................................................................................... 1.0w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. pins with bus hold are identified in the pin description. 5. this specification does not apply to bi-directional functionalities with bus hold.
pi74fct16823t/162823/162h823t 18-bit registers 4 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16823t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C3.0 ma 2.5 3.5 v i oh = C15.0 ma 2.4 3.5 i oh = C32.0 ma 2.0 3.0 v ol output low voltage v cc = min., v in = v ih or v il i ol = 64 ma 0.2 0.55 v i off power down disable v cc = 0v, v in or v out 4.5v 100 a pi74fct162823t/162h823t output drive characteristics (over the operating range) parameters description test conditions (1) min. typ (2) max. units v oh output high voltage v cc = min., v in = v ih or v il i oh = C24.0 ma 2.4 3.3 v v ol output low voltage v cc = min., v in = v ih or v il i ol = 24 ma 0.3 0.55 v i odl output low current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) 60 115 150 ma i odh output high current v cc = 5v, v in = v ih or v il , v out = 1.5v (3) C60 C115 C150 ma notes: 1. for max. or min. conditions, use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vcc = 5.0v, +25c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the test should not exceed one second. 4. this parameter is determined by device characterization but is not production tested. capacitance (t a = 25c, f = 1 mhz) parameters (4) description test conditions typ max. units c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 5.5 8 pf
pi74fct16823t/162823/162h823t 18-bit registers 5 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice. 2. typical values are at vcc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at vcc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the icc formula. these limits are guaranteed but not tested. 6. i c =i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v). d h = duty cycle for ttl inputs high. n t = number of ttl inputs at d h . i ccd = dynamic current caused by an input transition pair (hlh or lhl). f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f . all currents are in milliamps and all frequencies are in megahertz. power supply characteristics parameters description test conditions (1) min. typ (2) max. units i cc quiescent power v cc = max. v in = gnd 0.1 500 a supply current or v cc d i cc supply current per v cc = max. v in = 3.4v (3) 0.5 1.5 ma input @ ttl high i ccd supply current per v cc = max., v in = v cc 75 120 a/ input per mhz (4) outputs open v in = gnd mhz x oe = xclken = gnd one input toggling 50% duty cycle i c total power supply v cc = max., v in = v cc 0.8 2.7 ma current (6) outputs open v in = gnd f cp = 10 mh z 50% duty cycle v in = 3.4v 1.3 3.2 x oe = xclken = gnd v in = gnd f i = 5 mh z one bit toggling v cc = max., v in = v cc 4.2 7.1 (5) outputs open v in = gnd f cp = 10 mh z 50% duty cycle v in = 3.4v 9.2 22.1 (5) x oe = xclken = gnd v in = gnd eighteen bits toggling f i = 2.5 mh z 50% duty cycle
pi74fct16823t/162823/162h823t 18-bit registers 6 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct16823t switching characteristics over operating range 16823at 16823bt 16823ct 16823dt 16823et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 10.0 1.5 7.5 1.5 6.0 1.5 5.0 1.5 4.4 ns t phl x clk to x q x r l = 500 w c l = 300 pf (3) 1.5 20.0 1.5 15.0 1.5 12.5 1.5 8.5 1.5 8.0 ns r l = 500 w t phl propagation delay c l = 50 pf 1.5 14.0 1.5 9.0 1.5 8.0 1.5 5.0 1.5 4.4 ns x clr to x q x r l = 500 w t pzh output enable time c l = 50 pf 1.5 12.0 1.5 8.0 1.5 7.0 1.5 4.8 1.5 4.4 ns t pzl x oe to x q x r l = 500 w c l = 300 pf (3) 1.5 23.0 1.5 15.0 1.5 12.5 1.5 10.0 1.5 9.0 ns r l = 500 w t phz output disable time (3) c l = 5 pf (3) 1.5 7.0 1.5 6.5 1.5 6.2 1.5 5.0 1.5 4.0 ns t plz x oe to x q x r l = 500 w c l = 50 pf 1.5 8.0 1.5 7.5 1.5 6.5 1.5 5.0 1.5 4.0 ns r l = 500 w t su setup time high or c l = 50 pf 4.0 3.0 3.0 3.0 1.5 ns low, x d x to x clk r l = 500 w t h hold time high or 2.0 1.5 1.5 1.5 0 ns low, x d x to x clk t su setup time high or 4.0 3.0 3.0 3.0 2.5 ns low, x clken to x clk t h hold time high or 2.0 0 0 0 0 ns low, x clken to x clk t w xclk pulse width 7.0 6.0 6.0 6.0 3.0 ns high or low (3) t w xclr pulse width low (3) 6.0 6.0 6.0 6.0 3.0 ns t rem recovery time (3) 6.0 6.0 6.0 6.0 3.0 ns x clr to x clk t sk ( o ) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design.
pi74fct16823t/162823/162h823t 18-bit registers 7 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162823t switching characteristics over operating range 162823at 162823bt 162823ct 162823dt 162823et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 10.0 1.5 7.5 1.5 6.0 1.5 5.0 1.5 4.4 ns t phl x clk to x q x r l = 500 w c l = 300 pf (3) 1.5 20.0 1.5 15.0 1.5 12.5 1.5 8.5 1.5 8.0 ns r l = 500 w t phl propagation delay c l = 50 pf 1.5 14.0 1.5 9.0 1.5 8.0 1.5 5.0 1.5 4.4 ns x clr to x q x r l = 500 w t pzh output enable time c l = 50 pf 1.5 12.0 1.5 8.0 1.5 7.0 1.5 4.8 1.5 4.4 ns t pzl x oe to x q x r l = 500 w c l = 300 pf (3) 1.5 23.0 1.5 15.0 1.5 12.5 1.5 10.0 1.5 9.0 ns r l = 500 w t phz output disable time (3) c l = 5 pf (3) 1.5 7.0 1.5 6.5 1.5 6.2 1.5 5.0 1.5 4.0 ns t plz x oe to x q x r l = 500 w c l = 50 pf 1.5 8.0 1.5 7.5 1.5 6.5 1.5 5.0 1.5 4.0 ns r l = 500 w t su setup time high or c l = 50 pf 4.0 3.0 3.0 3.0 1.5 ns low, x d x to x clk r l = 500 w t h hold time high or 2.0 1.5 1.5 1.5 0 ns low, x d x to x clk t su setup time high or 4.0 3.0 3.0 3.0 2.5 ns low, x clken to x clk t h hold time high or 2.0 0 0 0 0 ns low, x clken to x clk t w xclk pulse width 7.0 6.0 6.0 6.0 3.0 ns high or low (3) t w xclr pulse width low (3) 6.0 6.0 6.0 6.0 3.0 ns t rem recovery time (3) 6.0 6.0 6.0 6.0 3.0 ns x clr to x clk t sk ( o ) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design.
pi74fct16823t/162823/162h823t 18-bit registers 8 ps2040a 03/11/96 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi74fct162h823t switching characteristics over operating range 162h823at 162h823bt 1628h23ct 162h823dt 162h823et com. com. com. com. com. parameters description conditions (1) min max min max min max min max min max unit t plh propagation delay c l = 50 pf 1.5 10.0 1.5 7.5 1.5 6.0 1.5 5.0 1.5 4.4 ns t phl x clk to x q x r l = 500 w c l = 300 pf (3) 1.5 20.0 1.5 15.0 1.5 12.5 1.5 8.5 1.5 8.0 ns r l = 500 w t phl propagation delay c l = 50 pf 1.5 14.0 1.5 9.0 1.5 8.0 1.5 5.0 1.5 4.4 ns x clr to x q x r l = 500 w t pzh output enable time c l = 50 pf 1.5 12.0 1.5 8.0 1.5 7.0 1.5 4.8 1.5 4.4 ns t pzl x oe to x q x r l = 500 w c l = 300 pf (3) 1.5 23.0 1.5 15.0 1.5 12.5 1.5 10.0 1.5 9.0 ns r l = 500 w t phz output disable time (3) c l = 5 pf (3) 1.5 7.0 1.5 6.5 1.5 6.2 1.5 5.0 1.5 4.0 ns t plz x oe to x q x r l = 500 w c l = 50 pf 1.5 8.0 1.5 7.5 1.5 6.5 1.5 5.0 1.5 4.0 ns r l = 500 w t su setup time high or c l = 50 pf 4.0 3.0 3.0 3.0 1.5 ns low, x d x to x clk r l = 500 w t h hold time high or 2.0 1.5 1.5 1.5 0 ns low, x d x to x clk t su setup time high or 4.0 3.0 3.0 3.0 2.5 ns low, x clken to x clk t h hold time high or 2.0 0 0 0 0 ns low, x clken to x clk t w xclk pulse width 7.0 6.0 6.0 6.0 3.0 ns high or low (3) t w xclr pulse width low (3) 6.0 6.0 6.0 6.0 3.0 ns t rem recovery time (3) 6.0 6.0 6.0 6.0 3.0 ns x clr to x clk t sk ( o ) output skew (4) 0.5 0.5 0.5 0.5 0.5 ns notes: 1. see test circuit and wave forms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. this parameter is guaranteed but not production tested. 4. skew between any two outputs, of the same package, switching in the same direction. this parameter is guaranteed by design. pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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